SOCS ENABLED BY ADVANCED GATE ARRAYS "The Perfect Balance Between Price and Performance" Santa Clara, CA -- March 3, 2003 - Speaking at the recent Institution of Electrical Engineers (IEE) System-on-Chip Professional Network launch, Dr. Stephen Bateman - VP of Engineering and R&D for Chip Express and Fellow of the IEE - commented, "Advanced Gate Arrays are an enabling technology for SoC implementation delivering the perfect balance of performance and price – the driving issues constraining SoC development." The launch event, held at the IEE’s central London headquarters, was marked by speeches by Sir Robin Saxby, Chairman of ARM, and Matthew Woolf, CTO of Pogo Mobile Solutions. Later, Lord Sainsbury of Turville, Parliamentary Under-Secretary of State for Science and Innovation, addressed a full house, welcoming the initiative as timely and valuable. Stephen Bateman has been a driving force and member of the IEE SoC professional network committee. He agreed with earlier speakers who commented that SoCs should not be regarded as a costly or hard-to-implement technology. Chip Express’ Advanced Gate Arrays, details Bateman, are attractive to established companies looking for the most cost-effective solution, as well as emerging businesses that need to prove the viability of their concept with a real production run, without spending all the seed and Series B investment capital in one go. Chip Express delivers silicon for worldwide applications running from a few thousand pieces and up in a choice of process geometries. "Using advanced gate arrays eliminates the need for expensive mask sets demanded by standard cell ASICs," he explained. "Development time can also be significantly reduced, yet the performance and density is much better than FPGAs." Bateman joined Chip Express - the Advanced Gate Array Cost Leader – in January 2003. The company’s patented advanced gate array technology, supported by its internally developed software tools and I/O cells, enables the company to design and manufacture SoCs using customised masks for only the top two metal mask layers in a device that can contain more than 30 mask layers using a standard CMOS process, while maintaining speed, power and size characteristics that are competitive with other types of ASIC design. www.chipexpress.com www.parkerpricevc.com CONTACT US    |    © PPVC 2001. All rights reserved.